1528 Jobs in Greater Bengaluru Area - Page 4

Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore Senior Physical Verification Lead Engineer Experience: 6+ years BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows for power, Ansys Redhawk /Cadence Voltus experience is must Experience – 6+ years Well versed with the power grid design and power calculation methodologies Role involves tasks in estimating power using industry standard tool , designing power grid , analyze power grid, doing static IR drop, dynamic IR drop Understanding custom placement/routing using semi-automatic/manual method , Should have worked on Physical Verification checks for Low Power SoC (DRC, ERC, LVS, ANT, ESD, DFM) Physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Good automation skills in PERL, TCL and EDA tool-specific scripting Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Experience : 4.00 + years Salary : INR 2500000-4000000 / year (based on experience) Shift : (GMT+05:30) Asia/Kolkata (IST) Opportunity Type : Hybrid (Bengaluru) Placement Type : Full time Permanent Position (*Note: This is a requirement for one of Uplers' client - PharmEasy) What do you need for this opportunity? Must have skills required: Java, System Design, HLD, LLD, Distributed Systems PharmEasy is Looking for: Job Description: WE ARE HIRING! Founded 2012, at API Holdings, our vision is bold and clear: To Build India’s Largest Digital Healthcare Platform. We are the driving force behind some of India’s most trusted healthcare brands—including PharmEasy, Ascent, Retailio, Thyrocare, DocOn, and Aknamed. Together, we are creating a connected healthcare ecosystem that empowers every Indian to access quality care—anytime, anywhere. From teleconsultations and diagnostics to e-pharmacy, hospital supply chain management, and digital health records, our platform is engineered to serve every stakeholder in the healthcare journey. We're not just solving for convenience—we're solving for reach, equity, and real impact. Our people are at the heart of this transformation. We believe in enabling our teams to take ownership and providing equal opportunity by challenging the status quo to grow in a fast-paced, impact-driven environment. If you're passionate about healthcare, product innovation, or creating scalable tech that improves lives—this is where your purpose meets potential. Business & Brands: Join us at PharmEasy: Launched in 2015, PharmEasy is a consumer healthcare “super app.” Started with the sole purpose of making healthcare accessible and affordable to all, PharmEasy today is India's leading and most trusted online healthcare aggregator in the country. We provide on-demand, home-delivered access to a wide range of prescription pharmaceuticals, diagnostic test services, OTC pharmaceuticals, and other consumer healthcare products, thereby serving your healthcare needs. Through our services, we ensure access to the best and most genuine health products, with the highest savings in the shortest time. Today, we deliver medicines in 1000+ cities in India, covering 19000+ pin codes. We offer diagnostic test services across Mumbai (including Thane, Navi Mumbai, Kalyan & Dombivli), Delhi (with Noida, Gurgaon, Faridabad & Ghaziabad), Chennai, Pune, Ahmedabad, Gandhi Nagar, Surat, Vadodara, Lucknow, Kolkata, Hyderabad, Bengaluru, and Jaipur. SIMPLIFYING HEALTHCARE, IMPACTING LIVES Tech-enabled Hospital Supplies Procurement India’s Largest Online Pharmacy Marketplace One of India’s Largest Pharma Platform, connecting Pharmacies with Distributors India's Largest Diagnostics Test Provider by Volumes Responsibilities RESEARCH, DESIGN, ARCHITECT, AND BUILD HIGHLY RELIABLE, AVAILABLE, AND SCALABLE SOLUTIONS CAPABLE OF HANDLING MILLIONS OF API CALLS ACROSS DISTRIBUTED SYSTEMS. LEAD THE TECHNICAL DESIGN AND IMPLEMENTATION OF COMPLEX SYSTEMS, APPLYING ADVANCED DESIGN PATTERNS AND ARCHITECTURAL BEST PRACTICES. ADOPT AI TO DELIVER CUSTOMER-FACING, COST-EFFECTIVE SOLUTIONS, IMPROVING NPS. OWN LARGE TECHNICAL DELIVERABLES AND MAINTAIN END-TO-END ACCOUNTABILITY FOR THE FUNCTIONAL SERVICES YOUR TEAM DELIVERS. DRIVE THE TECHNICAL ROADMAP IN COLLABORATION WITH PRODUCT AND BUSINESS TEAMS, ENSURING ALIGNMENT WITH ORGANIZATIONAL GOALS. BREAK DOWN AMBIGUOUS PROJECTS INTO ACTIONABLE TASKS AND MULTIPLE SPRINTS, PROVIDING ACCURATE DELIVERY ESTIMATES AND CLEAR TECHNICAL DIRECTION. LEAD BY EXAMPLE; MENTOR, COACH, AND GUIDE TEAM MEMBERS ON STRUCTURED PROBLEM-SOLVING, DEVELOPMENT BEST PRACTICES, AND CAREER GROWTH. PLATFORMIZE COMPONENTS AS LIBRARIES, UTILITIES, AND SERVICES TO PROMOTE REUSE AND STANDARDIZATION ACROSS TEAMS. MONITOR OPERATIONAL METRICS, ESTABLISH SLAS FOR SYSTEM PERFORMANCE, AND PROACTIVELY ADDRESS RELIABILITY AND SCALABILITY CONCERNS. COORDINATE INCIDENT RESPONSE AND LEAD ROOT CAUSE ANALYSIS FOR PRODUCTION ISSUES, DRIVING CONTINUOUS IMPROVEMENT. IMPLEMENT AND ENFORCE CODE QUALITY STANDARDS, REVIEW PROCESSES, AND TECHNICAL DOCUMENTATION PRACTICES. CONCEPTUALIZE AND DEVELOP PROTOTYPES QUICKLY TO VALIDATE TECHNICAL APPROACHES AND DE-RISK SOLUTIONS. COLLABORATE ACROSS FUNCTIONS AND TEAMS TO DESIGN AND IMPLEMENT END-TO-END SOLUTIONS. PROACTIVELY IDENTIFY AND MITIGATE TECHNICAL RISKS, LIMITATIONS, AND BOTTLENECKS. Requirements BTECH OR MTECH IN COMPUTER SCIENCE OR A RELATED TECHNICAL DISCIPLINE. EXPERTISE IN AT LEAST ONE TECHNOLOGY STACK (JAVA, PYTHON, NODE.JS, GOLANG), WITH PROFICIENCY IN MULTIPLE LANGUAGES/FRAMEWORKS. EXPERIENCE ARCHITECTING AND BUILDING COMPLEX, SCALABLE SOLUTIONS AND MANAGING MULTI-SYSTEM INTERACTIONS. STRONG OBJECT-ORIENTED DESIGN SKILLS WITH A DEEP UNDERSTANDING OF DESIGN PATTERNS, REST, DISTRIBUTED SYSTEMS, AND ASYNCHRONOUS COMMUNICATION. CAN PLAY THE ROLE OF AI ENGINEER, EVALUATE MULTIPLE POSSIBILITIES, AND IDENTIFY THE BEST MODELS FOR THE JOB AT HAND. EXPERIENCE IN ADOPTING AI IN THE SDLC PROCESS. PROVEN ABILITY TO BUILD REUSABLE CODE LIBRARIES, FRAMEWORKS, AND PLATFORM COMPONENTS. TRACK RECORD OF BUILDING AND DELIVERING MISSION-CRITICAL, 24X7 PRODUCTION SYSTEMS. STRONG KNOWLEDGE OF NON-FUNCTIONAL REQUIREMENTS (SCALABILITY, SECURITY, PERFORMANCE, RELIABILITY). EXPERIENCE MONITORING AND OPTIMIZING SYSTEM PERFORMANCE METRICS. ABILITY TO BREAK DOWN COMPLEX REQUIREMENTS INTO ACTIONABLE TASKS WITH ACCURATE ESTIMATES. EXCELLENT COMMUNICATION SKILLS, WITH THE ABILITY TO WRITE COMPREHENSIVE TECHNICAL DOCUMENTATION AND PRESENT TO STAKEHOLDERS. EXPERIENCE LEADING MULTI-ENGINEER PROJECTS, MENTORING JUNIOR TEAM MEMBERS, AND INFLUENCING CROSS-TEAM TECHNICAL DECISIONS. PROFICIENCY WITH AGILE METHODOLOGIES (SCRUM), TDD, AND CI/CD PIPELINES. DEMONSTRATED ABILITY TO BALANCE TECHNICAL EXCELLENCE WITH BUSINESS PRIORITIES. STRONG PROBLEM-SOLVING SKILLS WITH A DATA-DRIVEN APPROACH TO DECISION-MAKING. WHY JOIN US? FOLLOW US ON: API HOLDINGS PHARMEASY https://www.linkedin.com/company/api-holdings https://www.linkedin.com/company/pharmeasy How to apply for this opportunity? Step 1: Click On Apply! And Register or Login on our portal. Step 2: Complete the Screening Form & Upload updated Resume Step 3: Increase your chances to get shortlisted & meet the client for the Interview! About Uplers: Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement. (Note: There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well). So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you!

GLOBAL MNC: Location: Greater Bengaluru Area Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. It will continue to integrate the latest electronic and electrical architecture (E/EA) designs from automakers, realize the demands of the next-generation software-defined vehicle, and apply a chip design-oriented, human-centric service-oriented architecture (SOA) to the automotive field. This approach aims to meet the diverse needs of users and provide consumers with a new user experience. JOB DESCRIPTION: We are seeking a skilled Design for Test (DFT) Architect/Lead/Manager to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive industry. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards. Key Responsibilities: - DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive applications to ensure high quality and reliability. - Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with automotive testing standards. - Team Leadership: Lead a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities. - Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs. - Collaboration: Work closely with design, validation, and manufacturing teams to align DFT strategies with overall product goals and requirements. - Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262). - Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness. - Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team. Qualifications: - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. - 10+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications. - Proven experience leading DFT teams and managing complex projects. - In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation. - Familiarity with automotive industry standards and regulations (e.g., ISO 26262). - Proficiency in using DFT tools and EDA software. - Strong problem-solving skills and ability to work collaboratively in a fast-paced environment. - Excellent communication skills, both verbal and written. Contact: Sumit S. B. Email: sumit@mulyatech.com Mulya Technologies www.mulyatech.com "Mining the Knowledge Community"

Principal / Staff Design Verification Engineers Bangalore Founded in 2023,by Industry veterans HQ in California,US Location: Greater Bengaluru Area Company Description We are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI. Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision. Job Description The verification Engineer position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You will be responsible for RTL SoC/Subsystem verification of ARM-based SoCs, and work on industry-standard verification methodologies like UVM, Portable Stimulus, and Formal verification flows. You will report to the Director of Engineering (Verification). Design Verification Engineers Deep expertise and hands-on experience in developing UVM, SV testbench components, Checkers, Scoreboard and Stimulus Experience in defining test plans and developing directed/constrained random tests to achieve Verification Coverage, Prior experience and knowledge of APB/AXI/CHI bus protocols, Serial peripherals (eg: I2C, SPI), I/O Interfaces (PCIe,/CXL/ Ethernet), Memory (DDR/LPDDR/HBM) Architectural Domain knowledge - Processors, Memory, Coherency, Experience in working with repository management tools like Bitbucket/ Jenkins and bug-tracking tools like JIRA. BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent with 5-15 + years of industrial experience. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore Job Requirements • BE/ME with 12 years of experience • Knowledge of MOS transistors and analog circuit design • Knowledge of complex AC/DC analysis (poles, zeros, compensation), loop dynamics and feedback systems • Knowledge of device physics and CMOS/BiCMOS fabrication processes • Previous design experience with complex analog and mixed signal design blocks • Knowledge in signals, systems and transforms • Understanding of the end to end design flow from product definition to high volume manufacturing • Understanding of layout tradeoffs for performance and size • Knowledge of circuit simulation tools, layout verification tools, modelling tools, and UNIX Additional Skills (one or more of these are highly desirable) • Previous design experience with transceivers, power management circuits/systems, LDOs, high precision current/voltage references, regulators, ring oscillators, level shifters etc • Previous experience leading high precision analog ICs and/or sub-systems • Knowledge of high voltage processes and design in BCD and/or SOI type processes • MOS Device modeling skills (noise, excess thermal noise, DIBL) • System knowledge (e.g., isolators) and design skills in system modeling • Good written and verbal presentation skills Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore Experience : 7+ Years Work location : Bangalore Well versed with the timing closure (STA), timing closure methodologies. Pre/Post-layout constraint development to timing closure. Handshake with the design team and develop functional/DFT constraints. IP level constraint integration. Multi-voltage/Switching aware corner definitions. RC/C model selection understanding. Abstraction expertise like Hyperscale/ILM/ETM. RC Balancing and scaling analysis of full chip clock. RC Balancing and scaling analysis of critical data paths. Good automation skills in PERL, TCL and EDA tool-specific scripting. DMSA @ full chip and custom scripts for timing fixes Qualification: BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design. Detailed knowledge of EDA tools and flows, Tempus/Primetime experience is must. Experience – 7+ years. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.omnidesignte.com Principal Applications Engineer US Based Start-up founded by Industry Veterans who have PhDs from MIT Location; Bangalore Principal Applications Engineer BANGALORE /BUSINESS /FULL-TIME We are looking for a dynamic Staff Applications Engineer with pre-sales and/or post-sales experience delighting customers. The ideal candidate in this role is an engineer with experience in mixed-signal design and its application in products such as 5G, automotive/ADAS, AI, wireline communications, etc. Job Responsibilities Assist customers in adopting our IP through training & demos, presentations, solving technical issues and leading technical engagements Understanding of customer’s analog and mixed-signal design challenges, especially at advanced process nodes, and guiding them in refining their requirements and successfully integrating our IP in their products. Work with Sales to identify new opportunities, prioritize them and develop winning sales strategies. Communicate customer requirements and feedback to marketing and engineering for issue resolution and to improve product features and quality. Help the team in managing customer priorities and trade-offs. Qualifications Solid understanding of IC design technology and foundry process/methodology in analog layouts domain including a very good understanding of FinFET technology. Experience in high-performance mixed-signal design in advanced CMOS processes. Familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converters and their use in leading edge designs. Experience in conducting technical presentations and training, as well as product demos to customers, including development of customized presentations and other collateral. Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations. Must have ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. Should be able to seek help proactively as well as share knowledge. Education/Experience Education Requirements: BS/MS in Electrical Engineering Experience Requirements: 7-10 years’ experience Some travel will be required and necessary We are looking for trailblazers ... We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by our IP cores and the rapidly emerging semiconductor embedded design business ecosystem. , we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our Design’s vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are an equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence.

Large Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore Job Requirements • BE/ME with 12 years of experience • Knowledge of MOS transistors and analog circuit design • Knowledge of complex AC/DC analysis (poles, zeros, compensation), loop dynamics and feedback systems • Knowledge of device physics and CMOS/BiCMOS fabrication processes • Previous design experience with complex analog and mixed signal design blocks • Knowledge in signals, systems and transforms • Understanding of the end to end design flow from product definition to high volume manufacturing • Understanding of layout tradeoffs for performance and size • Knowledge of circuit simulation tools, layout verification tools, modelling tools, and UNIX Additional Skills (one or more of these are highly desirable) • Previous design experience with transceivers, power management circuits/systems, LDOs, high precision current/voltage references, regulators, ring oscillators, level shifters etc • Previous experience leading high precision analog ICs and/or sub-systems • Knowledge of high voltage processes and design in BCD and/or SOI type processes • MOS Device modelling skills (noise, excess thermal noise, DIBL) • System knowledge (e.g., isolators) and design skills in system modelling • Good written and verbal presentation skills Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

TITLE: Design Verification Engineer LOCATION: GREATER BENGALURU AREA Company Description With a strong focus on innovation and over two decades of experience, we deliver tailored AI-powered solutions across industries and global markets. Large Semiconductor Service Organization with revenue over 600 Million USD Job Description · 8+ years of design verification experience. · MS (or higher) in EE/EC/ECC Engineering · As a member of the Design Verification [ Pre-Silicon DV ] Team : You will be responsible for verification of various IP’s and/or SoC. · Candidate must be self-motivated and capable of working independently or as part of a team · You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. · You will also assist with developing test-plans, debugging failures and analyzing coverage information. · Must have excellent knowledge of computer architecture and design verification fundamentals · Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies · Must have experience in developing complex test bench in System Verilog using OVM/ UVM methodology · Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol · Experience in Low Power Simulation/UPF setup, debug low power simulation failures. · Exposure to scripting languages like Perl, Unix shell or similar languages · Good to have some experience with assembly language programming required · Excellent written and oral communication skills necessary Hands-on experience in PCIe MAC, OR USB MAC OR Bluetooth MAC OR Wifi 802.11 MAC layer protocol Contact Sumit S. B. sumit@mulyatech.com www.mulyatech.com "Mining the Knowledge Community" Practice Head(Talent Acquisition. Semiconductors Domain)

Senior Chip Lead /Chip Lead (Sr Director / Director) Hyderabad A Hyderabad based SoC Turnkey design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads – eventually cascading into block specifications. Make PPA decisions for the chip. Defining multiple development checkpoints – for IP/SoC Design/DV/PD Come up with overall project plan and cascaded schedule details for other teams Work with Analog/Digital IP teams to laydown integration details for the IPs. Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams. Define the sign-off criteria for the device. Define the SoC verification plan items/scenarios to be covered. Assist/Review the micro architecture definition for digital blocks Define RTL Quality gate criteria for integration – Lint/CDC/ Drive the timing constraints/timing analysis/closure activities. Define the DFT targets for the chip and cascade that into activities needed on the DFT front. Work with PD enginers to get the physical design closure. Handle tapeout formalities Qualifications: Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort. Proven ability to develop architecture and micro-architecture from specifications. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Top 100 Global Semiconductor MNC in the world Principal / Staff Design Verification Engineer Bangalore Description We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities. Primary Responsibilities Inclu de: Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practi ces.Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective act ion.Overall, responsible for verification of ASIC designs To include such things as:Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage,debug failures and providefeedback to the designt eam.Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible forDebugging Designs for High throughput, Low Latency of Pipeline and DynamicPower Management at full system le vel.Setup Verification Regression suites at RTL Level & Corresponding NetlistLevel after Synthesis to test any/all Cornercase conditi ons.Work closely with design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benc hes.Work closely with Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timelyand accurate deliverables with customers withinsched ules Necessary Qualificat ions: BS or MS in Computer Science or Electrical Engine ering.10+ years of industry experience bringing silicon ICs into high volume produ ction.Must have strong experience wit h UVM.Must have a full chip verification expe rienceExperience of leading a single pr oject.Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Rea lTime.Sound knowledge of ARMv8, interconnect, memory coherence and memory archite cturesFamiliarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verific ation)Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern gene ration Experience with low-level programming of systems in C/C++.Experienced in writing scripts in languages such as Perl, Python, an d Tcl.Functional understanding of constrained random verification process, functional coverage, and code coverage.Low power verification UPF Team player with excellent communication skills and the desire to take on diverse chall enges.Customer interaction Other Qualifications: Good knowledge of low power camera and imaging systems is a plus Experience with formal verification tools is a plus.CPU Security,Secure boot, SecureJTAG Familiarity with ARM architecture Familiarity with scripting/programming with Perl/Python, Tcl, C/C++ Contact:Uday Mulya Technologies muday_bhaskar@yahoo.com" Mining The Knowledge Community"

Top 100 Global Semiconductor MNC in the world Principal / Staff Design Verification Engineer Bangalore Description We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities. Primary Responsibilities Inclu de: Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practi ces.Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective act ion.Overall, responsible for verification of ASIC designs To include such things as:Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage,debug failures and providefeedback to the designt eam.Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible forDebugging Designs for High throughput, Low Latency of Pipeline and DynamicPower Management at full system le vel.Setup Verification Regression suites at RTL Level & Corresponding NetlistLevel after Synthesis to test any/all Cornercase conditi ons.Work closely with design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benc hes.Work closely with Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timelyand accurate deliverables with customers withinsched ules Necessary Qualificat ions: BS or MS in Computer Science or Electrical Engine ering.10+ years of industry experience bringing silicon ICs into high volume produ ction.Must have strong experience wit h UVM.Must have a full chip verification expe rienceExperience of leading a single pr oject.Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Rea lTime.Sound knowledge of ARMv8, interconnect, memory coherence and memory archite cturesFamiliarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verific ation)Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern gene ration Experience with low-level programming of systems in C/C++.Experienced in writing scripts in languages such as Perl, Python, an d Tcl.Functional understanding of constrained random verification process, functional coverage, and code coverage.Low power verification UPF Team player with excellent communication skills and the desire to take on diverse chall enges.Customer interaction Other Qualifications: Good knowledge of low power camera and imaging systems is a plus Experience with formal verification tools is a plus.CPU Security,Secure boot, SecureJTAG Familiarity with ARM architecture Familiarity with scripting/programming with Perl/Python, Tcl, C/C++ Contact:Uday Mulya Technologies muday_bhaskar@yahoo.com" Mining The Knowledge Community"

Principal / Staff Design Verification Engineers Bangalore Founded in 2023,by Industry veterans HQ in California,US Location: Greater Bengaluru Area Company Description We are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI. Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision. Job Description The verification Engineer position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You will be responsible for RTL SoC/Subsystem verification of ARM-based SoCs, and work on industry-standard verification methodologies like UVM, Portable Stimulus, and Formal verification flows. You will report to the Director of Engineering (Verification). Design Verification Engineers Deep expertise and hands-on experience in developing UVM, SV testbench components, Checkers, Scoreboard and Stimulus Experience in defining test plans and developing directed/constrained random tests to achieve Verification Coverage, Prior experience and knowledge of APB/AXI/CHI bus protocols, Serial peripherals (eg: I2C, SPI), I/O Interfaces (PCIe,/CXL/ Ethernet), Memory (DDR/LPDDR/HBM) Architectural Domain knowledge - Processors, Memory, Coherency, Experience in working with repository management tools like Bitbucket/ Jenkins and bug-tracking tools like JIRA. BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent with 5-15 + years of industrial experience. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Technology Expert, PCIe 7.0 & UCIe ( Senior Manager / Manager) www.omnidesigntech.com Location: Bengaluru / Hyderabad www.omnidesigntech.com Location- Bangalore About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Job Summary: Principal SerDes Technology Expert We are seeking a highly motivated and experienced Principal SerDes Technology Expert to lead the development of next-generation connectivity solutions. Your journey will begin by spearheading the design and optimization of high-performance Active Electrical Cables (AECs), enhancing electrical integrity and signal quality across demanding link budgets. Building on this foundation, you will architect and implement SerDes technology tailored for PCIe 7.0, tackling challenges such as lane equalization, jitter tolerance, and power efficiency. Finally, your work will expand into integrating cutting-edge optical interconnects and optocouplers, driving innovations in retimer technologies and hybrid signaling frameworks. This role directly impacts the performance and reliability of AI and cloud infrastructure—empowering massive data throughput, energy-efficient links, and scalable system architectures. Responsibilities: Lead the architecture and design of high-speed SerDes for PCIe 7.0, targeting data rates of 128 GT/s and beyond. Spearhead the development and integration of advanced optical interconnects and retimer solutions within our Smart Cable Modules™. Define and specify the requirements for mixed-signal SerDes PHYs, including transmitter (TX), receiver (RX), and clock and data recovery (CDR) circuits. Conduct in-depth analysis and simulation of high-speed channel performance, including signal integrity (SI) and power integrity (PI). Collaborate with cross-functional teams, including hardware design, firmware, and system validation, to ensure successful product development and bring-up. Stay at the forefront of industry standards and emerging technologies, particularly related to PCIe, CXL, and high-speed optical interconnects. Mentor junior engineers and provide technical leadership across the organization. Work closely with partners and vendors to evaluate and select key components. Qualifications: Required Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 10-15 years years of experience in high-speed SerDes design and development. Proven expertise in PCIe protocols, with direct experience in PCIe 4.0/5.0/6.0 design and a strong understanding of the upcoming PCIe 7.0 specification. In-depth knowledge of mixed-signal design, including experience with PAM4 signaling, equalization techniques (e.g., FFE, DFE), and clocking architectures. Hands-on experience with high-speed test and measurement equipment (e.g., oscilloscopes, BERTs, VNAs). Strong understanding of signal integrity principles and experience with simulation tools (e.g., HSPICE, ADS, Ansys). Preferred Qualifications: Master's or Ph.D. in a relevant technical field. Experience with the design and integration of optical interconnects, silicon photonics, or high-speed optoelectronics. Familiarity with the design of retimers and their application in Active Electrical Cables. Experience with high-level modeling of SerDes links using tools like MATLAB or Python. Knowledge of other high-speed protocols such as Ethernet, CXL, or NVLink. A track record of leading complex projects from concept to production. Excellent communication and interpersonal skills. We are seeking a highly skilled and experienced IP Design Engineer to join our team, focusing on the design, development, and validation of cutting-edge high-speed interface Intellectual Property (IP). The ideal candidate will have a strong background in complex digital and mixed-signal design, with a particular emphasis on interfaces such as UCIe, Die-to-Die (D2D), and various memory PHYs (DDR/LPDDR). Expertise in advanced clocking architectures including PLLs and DLLs is also essential. This role involves contributing to the full IP development lifecycle, from architectural definition and RTL design to silicon validation and post-silicon support, ensuring first- pass silicon success for critical products that enable next-generation data center interconnects. Key Responsibilities: • Design & Development: Architect, design, and implement high-speed interface IPs, including UCIe, D2D, DDR, and LPDDR PHYs. Contribute to the development of high-speed SerDes IP transceivers supporting rates like 100G PAM4 (106.25 Gbps), 50G PAM4 (53.125 Gbps), and 25G NRZ (26.5625 Gbps) for applications such as PCIe, Ethernet, and data center interconnects. • Clocking Design: Develop and optimize PLL (Phase-Locked Loop) and DLL (Delay- Locked Loop) circuits for high-speed clock generation and synchronization, ensuring low jitter and high accuracy. This includes experience with Fractional/Spread-spectrum/Integer Frequency synthesizers, LC VCOs, Multi- Modulus Dividers, Charge Pumps, LPFs, LDO regulators, and BGRs. • IP Development Lifecycle: Participate in the complete IP design flow, including architectural definition, specification development, RTL coding, synthesis, static timing analysis (STA), and collaborating on physical design activities (GDSII). 1 • Verification & Validation: Work closely with verification teams to define test plans, debug complex design issues, and lead pre-silicon and post-silicon validation efforts, including silicon bring-up and characterization .2 Implement features for deep in-cable diagnostics (e.g., eye metric readout, PRBS bit error rate, loopback modes), fleet management, and security for robust interconnect solutions. • Analog/Mixed-Signal Integration: Collaborate on the integration of analog and mixed-signal blocks within the PHYs, addressing complex integration challenges and optimizing for performance, power, and area (PPA). • Documentation: Create comprehensive design specifications, integration guidelines, and application notes for IP blocks.• Problem Solving: Debug and resolve complex design issues at various stages of the development cycle, including silicon debugging and fault isolation. • Standards Compliance: Ensure IP designs comply with industry standards (e.g., JEDEC for DDR/LPDDR, QSFP-DD/OSFP mechanical and common management interface specifications) and customer requirements. • Performance Optimization: Focus on achieving low-latency data paths (< 100 ns) and optimizing for lower power consumption in high-speed interconnect solutions. Required Qualifications: • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.3 • 15-25 years of experience in digital, mixed-signal, or analog IP design within the semiconductor industry. (Adjust X based on Senior/Principal level). • Proven experience with high-speed interface designs such as UCIe, D2D, DDR PHY, or LPDDR PHY. • Demonstrated experience in the design and optimization of PLLs and/or DLLs, including various types of frequency synthesizers and clock generation circuits. • Familiarity with the entire IP development flow from architectural concept to silicon validation. • Strong understanding of signal integrity, power integrity, and layout considerations for high-speed designs, especially for PAM4 and NRZ signaling over copper cables. • Proficiency with industry-standard EDA tools for design, simulation, and analysis. • Experience with deep diagnostic features, security implementations (firmware security, unauthorized access prevention), and non-disruptive firmware updates for high-speed modules. • Excellent problem-solving skills and attention to detail. • Strong communication and collaboration skills to work effectively with cross- functional teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior Engineer, Package Design – Bengaluru, KA- India Top 100 Global Semiconductor MNC in the world Bangalore Description We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities. Senior Engineer, Package Design – Bengaluru, KA- India Responsibilities: The Package substrate design focus on signal and power integrities analyses as well as routing analyses. You will be reporting to the Director of Package Design (USA) and working very closely with Package design team in our parent company’s headquarters in Japan and Marketing and Engineering teams located in our Milpitas office during the pre/post sales process. This position requires a broad knowledge of package technology and design. Successful candidates will have a deep understanding and experience in the following areas: high performance build-up substrates, flip chip assembly or 2.5D packaging. Knowledge and experience in extracting/simulating package designs for Signal and Power integrities using tools such as HFSS, and/or ADS tools. Education: Bachelor’s degree in Electrical Engineering, or other semiconductor packaging related discipline MS is preferred Required Experience and Skills: 8 to 10 years of experience in semiconductor packaging design, modeling, extraction, and simulations Record of success in cross-functional team environment Good experience with Signal and power integrity tools for package level modeling/extraction/simulation Ability to work with Package Layout engineers. Strong presentation and communication skills Preferred Experience and Skills: Hands-on package design; high-speed Signal integrity and Power integrity and package decoupling caps optimizations, combined package and PCB Signal integrity and Power integrity Characterizations, impedance verification, high frequency s-parameters extraction, Hspice model, package Hspice and RLC model extraction and designs Hands-on high-speed package and PCB design for: high-speed Serdes 112 Gbps, PCIeX5 and 6, LPDDR4,5, Ethernet 25 GBps, power aware SI/PI analysis, up to 40 GHZ s-parameters extraction and verification Packaging+PCB high-speed interconnections timing analyses, eye-diagram and jitter budgeting calculation following the LPDDR JEDEC spec, or other highs-speed frequency domain s-parameters extraction following the base Spec of high-speed interconnect Hands-on PCB design; SI, PI analyses, decoupling caps optimizations, SI and PI Characterization and extractions, impedance verification, s-parameters verifications with lab measurements, Hspice model, PCB RLC model extraction and designs Packaging routing analyst, trace impedance analyses and package layout bump to ball analyses Package material characterization frequency dependent model; skin effects, smoothness, roughness, dielectric loss and dielectric constant PCB material characterization frequency dependent; routing degree of freedom Time domain analyses and jitter budgeting for PCIe2/3/4/5, Serdes 112 GBps, Ethernet 25 Gbps, LPDDR4/5X MIPI, high-speed frequency signaling Time domain analyses and budgeting model for LPDDR 3/4/5, LPDDRX 3/4/5/6 Bathtub curve and BER analyses of high speed signaling DDR frequency and time domains model and jitter analyses and path findings to improve package and PCB layout and improve high-speed interconnections Clk jitter analyses, routing, clk tree analyses Simulating multi-physics electro-thermal analysis Collateral packaging manufacturing and assembly rules Chip and package Reliability analyses Die+Pkg+pcb PDN model time and frequency, Impedance profile, AC droop, DC drop DC, etc. IR drop, and CPM (chip power model) die model using Redhawk and other tolls Core PI: simulation capability, tool/flow and past experience on measurement capability, lab tool set up. Contact:Uday Mulya Technologies muday_bhaskar@yahoo.com" Mining The Knowledge Community"

SENIOR FIELD APPLICATIONS ENGINEER Bangalore, INDIA Break through the data movement barrier We are a data-driven, software-defined, unified fabric boosts performance and scalability for SoCs and chiplets. We are a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services! Location: Bangalore, India SENIOR FIELD APPLICATIONS ENGINEER BENGALURU, INDIA About the role: If you are skilled and have experience as a Senior Field Applications Engineer, you will play a critical role in providing technical expertise and support to our customers. You will empower and guide them on designing and deploying our technologies into their products. You will work closely with our sales and engineering teams to understand customer requirements, troubleshoot technical issues, and deliver customized solutions that exceed expectations. Responsibilities: Serve as the primary technical point of contact for key customers, providing guidance and support throughout the product development lifecycle. Assist in the design and implementation of customized solutions to meet customer-specific requirements. Develop and deliver technical presentations, demonstrations, and training sessions to customers, partners, and internal teams. Provide timely resolution to customer inquiries, issues, and concerns, ensuring high levels of customer satisfaction. Stay current with industry trends, technologies, and standard methodologies to effectively advise customers on product development strategies. Skills and Experience: 10+ years of experience in a field application engineering or customer-facing technical role, with a master’s degree in electrical engineering, Computer Engineering, or related field. Experience in designing or supporting complex SoC, from architecture definition to tape-out, addressing implementation challenges on advanced process nodes. Understanding of RAS and reliability for enterprise and infrastructure markets is a plus. Understanding of functional safety standards and certification. Excellent communication and interpersonal skills, with the ability to effectively engage with customers, colleagues, and partners at all levels. The role will involve travel to customer sites and events. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Technical Director-Mixed Signal IC Design (High level Proficiency and Hand-on ) Top100 Global Semiconductor Organization HQ in California. Revenue over 200 Million USD Location: Bangalore Location: Bangalore, India Desired Education Level: Graduate / Doctorate and above Years of experience: MTech/M.S. with 16+ years of experience or Ph.D. with 13+ years We are a precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, We are changing the timing industry. . Job Summary Responsibilities: • Lead development of analog Mixed-signal IC and owns the top level • Supervise and review block designer work and hold design review • Work with cross-functional team to architect the chip for DFT • Closely work and support cross functional team for bench validation, qualification and final test development. • Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes • Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications • Perform transistor-level design and simulation using industry leading EDA tools • Lead comprehensive design reviews • Supervise Analog Circuit Physical Design Layout and edit layouts • Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release • Work closely with the verification team to define the verification matrix. • Have the ownership of the top-level schematic and run all the top-level analog simulation. • Participate in top-level AMS verification. Qualifications & Requirements (Education must be included): • MTech/M.S. with minimum 10 years of relevant experience or Ph.D. with 6 years of Relevant experience in Electrical Engineering • Provel track record of taking at least one analog-mixed signal part to high-volume production. • Proven track record at each stage of the following: • Circuit architecture development and technical feasibility studies • Writing detailed block-level specifications and review documents • Detailed design and simulation of some of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture • Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL • Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers • Extensive experience with post-layout extraction and verifications • Experience with validation, characterization, qualification, and adherence to production release criteria • Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital, verifications engineers • Ability to work independently and drive solutions to challenging problems Desired Characteristics & Attributes: • An “ownership” mind set focusing on the overall success of the business. • Can do” positive, enthusiastic attitude. • Demonstrated analytical and problem-solving skills. • Strong communication skills. • Ability to work in teams and collaborate effectively with people in different functions. • Ability to efficiently context – switch between multiple concurrent tasks. We are a Equal Opportunity Employer. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Top 100 Global Semiconductor MNC in the world Principal / Staff Design Verification Engineer Bangalore Description We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities. Primary Responsibilities Inclu de: Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practi ces.Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective act ion.Overall, responsible for verification of ASIC designs To include such things as:Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage,debug failures and providefeedback to the designt eam.Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible forDebugging Designs for High throughput, Low Latency of Pipeline and DynamicPower Management at full system le vel.Setup Verification Regression suites at RTL Level & Corresponding NetlistLevel after Synthesis to test any/all Cornercase conditi ons.Work closely with design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benc hes.Work closely with Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timelyand accurate deliverables with customers withinsched ules Necessary Qualificat ions: BS or MS in Computer Science or Electrical Engine ering.10+ years of industry experience bringing silicon ICs into high volume produ ction.Must have strong experience wit h UVM.Must have a full chip verification expe rienceExperience of leading a single pr oject.Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Rea lTime.Sound knowledge of ARMv8, interconnect, memory coherence and memory archite cturesFamiliarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verific ation)Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern gene ration Experience with low-level programming of systems in C/C++.Experienced in writing scripts in languages such as Perl, Python, an d Tcl.Functional understanding of constrained random verification process, functional coverage, and code coverage.Low power verification UPF Team player with excellent communication skills and the desire to take on diverse chall enges.Customer interaction Other Qualifications: Good knowledge of low power camera and imaging systems is a plus Experience with formal verification tools is a plus.CPU Security,Secure boot, SecureJTAG Familiarity with ARM architecture Familiarity with scripting/programming with Perl/Python, Tcl, C/C++ Contact:Uday Mulya Technologies muday_bhaskar@yahoo.com" Mining The Knowledge Community"

Top 100 Global Semiconductor MNC in the world Senior Engineer / Staff Design Verification Engineer Bangalore Description We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities. Primary Responsibilities Inclu de: Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practi ces.Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective act ion.Overall, responsible for verification of ASIC designs To include such things as:Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage,debug failures and providefeedback to the designt eam.Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible forDebugging Designs for High throughput, Low Latency of Pipeline and DynamicPower Management at full system le vel.Setup Verification Regression suites at RTL Level & Corresponding NetlistLevel after Synthesis to test any/all Cornercase conditi ons.Work closely with design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benc hes.Work closely with Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timelyand accurate deliverables with customers withinsched ules Necessary Qualificat ions: BS or MS in Computer Science or Electrical Engine ering.5-10+ years of industry experience bringing silicon ICs into high volume produ ction.Must have strong experience wit h UVM.Must have a full chip verification expe rienceExperience of leading a single pr oject.Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Rea lTime.Sound knowledge of ARMv8, interconnect, memory coherence and memory archite cturesFamiliarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verific ation)Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern gene ration Experience with low-level programming of systems in C/C++.Experienced in writing scripts in languages such as Perl, Python, an d Tcl.Functional understanding of constrained random verification process, functional coverage, and code coverage.Low power verification UPF Team player with excellent communication skills and the desire to take on diverse chall enges.Customer interaction Other Qualifications: Good knowledge of low power camera and imaging systems is a plus Experience with formal verification tools is a plus.CPU Security,Secure boot, SecureJTAG Familiarity with ARM architecture Familiarity with scripting/programming with Perl/Python, Tcl, C/C++ Contact:Uday Mulya Technologies muday_bhaskar@yahoo.com" Mining The Knowledge Community"

Principal / Staff Design Verification Engineer Bangalore Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they're looking for passionate individuals to join a seasoned and dynamic team. Positions Available in Bengaluru, India/fully onsite Principal Design Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. Qualifications and Preferred Skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 6-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol is a plus Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs Experience with formal verification techniques, emulation platforms is a plus Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com

Area(s) of responsibility Senior Test Lead - Ecommerce Job Title: UAT Senior Test Lead – eCommerce Platform Location: Bangalore Employment Type: Full-Time Experience Level: 10+ years in QA/UAT, with 1+ years in eCommerce domain Job Summary We are seeking a highly experienced UAT Test Leader to lead the User Acceptance Testing efforts for our eCommerce platform. The ideal candidate will ensure that all business requirements are met, and the platform delivers a seamless user experience across web and mobile channels. You will collaborate with cross-functional teams including business analysts, developers, QA, and product owners to validate end-to-end functionality before production release. Key Responsibilities UAT Planning & Strategy Define UAT scope, objectives, and success criteria. Develop UAT test plans, schedules, and resource allocation. Align testing goals with business and customer expectations. Experience in Model based testing to achieve end to end testing objectives Test Case Management Oversee creation and execution of test cases based on business requirements. Ensure coverage of critical eCommerce flows (e.g., product search, cart, checkout, payment, returns). Defect Management Track, analyze, and escalate defects. Collaborate with development and QA teams for resolution. Stakeholder Communication Facilitate UAT sign-off and ensure stakeholder alignment. Environment & Data Setup Ensure UAT environment mirrors production. Manage test data preparation and validation. Compliance & Documentation Ensure adherence to regulatory standards, SOX approvals Maintain documentation of test results, issues, and resolutions. Required Skills & Qualifications Bachelor’s or Master’s degree in Computer Science, Engineering, or related field. Strong understanding of eCommerce platforms, customer journeys, and payment gateways. Hands on experience on Magento is Must have with in depth knowledge on Functional flow and Admin Flows Experience with JIRA, Confluence, TestRail, or similar tools. Familiarity with Agile, Scrum, methodologies. Excellent analytical, problem-solving, and communication skills. ISTQB, PMP, or similar certifications preferred. Preferred Experience 1+ years in UAT/Test Management roles for e-commerce platforms Experience in testing third-party integrations (e.g., payment processors, shipping APIs). Knowledge of automation tools and frameworks is a plus.

Company Description We suggest you enter details here Role Description This is a full-time remote role for a Data Analyst. The Data Analyst will be responsible for analyzing and interpreting complex data sets, developing data models, creating data visualizations, and providing insights to support data-driven decision-making. The role includes tasks such as gathering and cleaning data, performing statistical analyses, and effectively communicating findings to stakeholders. Qualifications Analytical Skills and Data Analytics abilities Experience with Statistics and Data Modeling Strong Communication skills for presenting data insights Proficiency with data analysis tools and software such as Excel, SQL, R, or Python Detail-oriented with strong problem-solving skills Ability to work independently and remotely Bachelor's degree in Data Science, Statistics, Computer Science, or a related field Experience in the cryptocurrency or financial industry is a plus

Founded: 2023, Bengaluru HQ Stage: Fast-growing (post–PMF, enterprise adoption by leading brands) Mission: Redefine performance marketing with AI — enabling digital marketing and growth teams to scale efficiently and profitably. Product: QScale , an AI-powered product feed enhancement platform trusted by Zalora, Swiggy Instamart, Flipkart, Snapdeal, Purplle, and ABFRL . QScale isn’t just a tool — it’s indispensable. Leaders love it so much they carry it with them to new companies. That’s product-market fit at its best. Join a high-energy, first-principles team of 15 builders. We’re radically open, bias towards action, and obsessed with creating industry-first breakthroughs. This is your chance to join a rocket ship at takeoff — shaping the next unicorn in AI. What You’ll Do Own the full enterprise sales cycle — from prospecting to closing large, complex deals. Consistently hit (and exceed!) monthly and quarterly targets. Build ICP lists, map accounts, and design GTM strategies for enterprise clients. Sell consultatively: understand client pain points and deliver tailored AI-driven solutions. Work directly with founders and product leaders to shape strategy and drive market expansion. Leverage your network to strengthen the pipeline and accelerate enterprise growth. Use insights and data to refine targeting and positioning. What We’re Looking For 3+ years of success in enterprise SaaS or tech sales . Proven track record of closing large enterprise deals. Strong ability to engage and influence C-level executives . Excellent communicator with crisp storytelling and persuasive pitch skills. Self-driven, target-oriented, thrives in early-stage ambiguity. Bonus: Exposure to martech, ecommerce, or adtech ecosystems. What You’ll Gain First-hand experience building a category-defining AI company . Ownership: shape our sales playbook and GTM engine from the ground up. Direct exposure to top-tier enterprise clients across India and SEA. Work with a high-caliber founding team (ex-Vedantu, Flipkart, Atomberg). Hyper-growth career trajectory as we scale from 15 → 150 people. How to Apply Send your CV and a short note about: Email: pranay@quantacus.ai) Compensation: Competitive salary + performance-driven incentives + early-stage equity opportunities.

Company Description We suggest you enter details here. Role Description This is a full-time hybrid role for a Field Sales Representative located in the Greater Bengaluru Area, with some work-from-home options. The Field Sales Representative will be responsible for generating leads, managing customer accounts, conducting sales visits, presenting products, negotiating contracts, and providing excellent customer service. The role also includes maintaining records of sales activities, achieving sales targets, and collaborating with the sales team and other departments. Qualifications Proven experience in Sales and Lead Generation Excellent Communication and Customer Service skills Knowledge of Sales Operations and sales techniques Strong negotiation and closing skills Ability to work independently and in a hybrid work environment Proficiency in using CRM software Bachelor's degree in Business, Marketing, or related field is a plus. Ability to travel within the Greater Bengaluru Area

Company Description At Novaspire Biosciences, we pride ourselves on being a trusted partner to the pharmaceutical industry, delivering comprehensive, high-quality clinical research services. We specialize in supporting pharmaceutical, biotechnology, medical device, and nutraceutical companies at every stage of the drug/product development lifecycle, from clinical studies Phase I to post-market surveillance. Our core services include pharmacovigilance, clinical trials, medical writing, bioequivalence study support, GxP consulting services & training, and imaging studies. With over 75 years of combined experience, our team provides solutions and streamlined processes to ensure efficient and effective research outcomes. Role Description • Organize, manage and maintain a highly compliant Pharmacovigilance (PV) system • Maintain awareness and ensure adherence to established and updated local and global processes and guidelines as well as national and international regulations and guidelines for pharmacovigilance. • Ensure PV business continuity and after hours availability. • Lead and coordinate internal and external PV audits and inspections. • Monitor PV system performance and compliance of partners and distributors. • Maintain expertise in country as well as worldwide regulations and guidelines and promote increased awareness of the legislative and regulatory environment in the country. • Accountable for all strategic PV activities • Active contribution to the activities relevant to the pharmacovigilance system to ensure monitoring of the safety profile • Act as the responsible contact person in the region, internally and externally, for safety-related aspects and PV. • Ensure internal regulatory/PV processes and procedures are well documented and support compliant regulatory/PV activities. • Perform other duties as assigned. Skills Required: • In depth knowledge of national/regional regulatory legislation and guidelines. • Knowledge of the pharmacovigilance regulations of all the countries. • Demonstrated ability to provide quality work using strong organizational, facilitation and interpersonal skills in a cross-functional team locally, within PV and externally. • Skilled at people management including overseeing and controlling outsourced vendor activities in a compliance/regulated field. • Capable of troubleshooting and managing multiple projects simultaneously. • Strong knowledge and understanding of medical terminology and clinical development processes • Rational approach to issues and their business implications, good problem solving and decision making skills. • Highly analytical with the ability to give attention to detail. • Excellent organizational skills and capable of working efficiently. • Possess an excellent interpersonal, verbal, and written communication skills. Minimum Requirements: • Minimum five years of working experience within the pharmaceutical industry and minimum five years within pharmacovigilance. • Degree / Advanced degree in medicine or in life sciences or equivalent experience • Excellent communication skills including proficiency in verbal and written English • Experience in other affiliate medical functions (e.g., Medical Affairs, Clinical Operations, Medical Information) or global clinical product development is considered advantageous. • Proficiency in Microsoft Word and Excel.